Synchronous SRAMs are a type of SRAM that is registered and accessed in accordance with externally generated clock signals. The clock signal provides for synchronous operation of the SRAM.
In memory design evolution, memory devices commonly increase in size by a factor of four from one generation to the next. For example, the next generation memory device after a 256K bit memory device is a 1M bit device. Following the 1M device is the 4M device, and so on. This fourfold generational jump in memory size leaves a significant gap in memory depth between generation sizes. For example, suppose that a 32K.times.36 memory device and a 128K.times.36 memory device are available, but a designer wants to implement an intermediate memory size, such as a 64K.times.36 memory device. The ability to achieve intermediate memory sizes is desirable because it affords system design flexibility without the drawback of over or under utilizing memory capacity.
One common technique for achieving memory depth expansion is by stacking two or more memory devices together and adding external logic to control them. This is not a favorable alternative, however, because it complicates system level design. It is more desirable to provide the intermediate memory device size without introducing external logic.
To avoid the use of external logic, another prior art approach employs two separate SRAM devices, where each device is equipped with an active low and an active high chip select. The two chip selects are internally logically combined so that one signal is used to selectively access one of the two synchronous SRAMs. One of the drawbacks in this design, however, is that there is no ability to operably disable both devices simultaneously or operate the devices in a pipelining mode (discussed below).
One specific type of synchronous SRAMs is a synchronous burst SRAM which is designed in systems to achieve higher SRAM performance. Synchronous burst SRAMs have an internal counter which facilitates internal addressing of typically two to four addresses for each externally generated address that is loaded into the memory device. The internal "burst" addresses can be generated more rapidly in comparison to externally generating the same addresses and then loading them into the memory device using conventional techniques. Accordingly, the burst SRAMs operate faster and achieve higher performance.
It is desirable and advantageous for synchronous burst SRAMs to facilitate a microprocessor-related function known as "address pipelining". In general, a microprocessor attached to the synchronous burst SRAM outputs an address and data strobe signal each time a new address is ready for input into the SRAM device. On occasions, it may be desirable to delay execution of that new address. For example, in a synchronous burst SRAM, it might be desirable to continue the burst addressing operation before accepting the next external address. Accordingly, the synchronous burst SRAMs must be capable of blocking or delaying operation on the new address (as indicated by the address and data strobe signal from the microprocessor) until the burst operation is completed.
It is also worth noting that achieving intermediate sizes in memories can be costly. The economies are best realized through the fourfold generational size increase. There is a continuing need to design intermediate memory sizes that are also inexpensive to manufacture.
The synchronous SRAM of this invention overcomes the above drawbacks by providing an intermediate memory depth without use of external logic. The novel synchronous SRAM also includes a pipelining mode and a power down mode without expensive components or circuitry.